1. Field of the Invention
The invention relates generally to a flash memory device and method of erasing the same, and more particularly to, a flash memory device in which a capacitor of a given capacitance is connected between a bit line connected to a drain region and a ground line within a flash cell array, and method of erasing the same. Therefore, the present invention can accelerate an increase of hot carriers generated in a diode reverse-bias state between the drain region and a semiconductor substrate upon an erase operation of the cell to prevent over-erase or non-erase of the cell by means of hot carriers and thus solve an over-erase problem of the cell without requiring additional pre-programming and verification operation, and additional post-programming and verification operation, thus reducing the time and power consumption in the cell erase operation.
2. Description of the Prior Art
The type of semiconductor memory devices is mainly classified into RAM (Random Access Memory) products such as DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory), and ROM (Read Only Memory). RAM is volatile since the data in RAM is lost in time but ROM is nonvolatile since the data in ROM is not lost. Also, the input/output speed of data in RAM is fast but the input/output speed of data in ROM is low. The ROM products include ROM, PROM (Programmable ROM), EPROM (Erasable Programmable ROM) and EEPROM (Electrically Erasable Programmable ROM). Of the ROM products, there is a trend that a demand for EEPROM into/from which data can electrically programmed and erased is increased. The EEPROM or a flash EEPROM having a batch erase function has a stack type gate structure in which a floating gate electrode and a control gate electrode are stacked.
The flash memory cell has been widely used in portable electronics such as notebooks, PDAs, cellular phones and the like, and computer BIOS and printer or the like. In view of a circuit, the type of the flash memory cell is classified into a NAND type suitable for higher integration and a NOR type suitable for high-speed operation. In the NAND type flash memory cell, n number of cell transistors is serially connected to form a string and a plurality of strings are in parallel connected between bit lines and ground lines. On the other hands, in the NOR type flash memory cell, respective cell transistors are in parallel connected between bit lines and the ground lines.
The structure and operation of a basic NOR type flash memory cell will be below described by reference to FIGS. 1 and 2. FIG. 1 is an equivalent circuit diagram of a conventional flash memory cell array, and FIG. 2 is a vertical cross-sectional view of the memory cell shown in FIG. 1.
Referring now to FIG. 1, a plurality of memory cells MC are connected between a plurality of word lines W/L and a plurality of bit lines B/L, which are orthogonal one another. A source region of each of the memory cells MC is connected to a common source line CSL.
A structure of the memory cells MC will be below described by reference to FIG. 2. A tunnel oxide film 11 of 100 xc3x85 in thickness is formed between a floating gate 12 and a semiconductor substrate 10. An interlayer dielectric film 13 of an oxide/nitride/oxide (ONO) structure having a high dielectric constant is formed between the floating gate 12 and a control gate 14 serving as the word lines W/L. In addition, source and drain regions 15 and 16 are formed to be self-aligned with the stack gate.
The NOR type flash memory cell performs a program operation using a channel hot electron (CHE) injection method and performs an erase operation using the F-N (Fowler-Nordheim) tunneling effect through a source or a bulk substrate.
First, the programming operation is one to store electrons in the floating gate 12 to increase the threshold voltage Vth of the cell MC from a voltage of around 2V being an initial Vth value to a voltage of about 7V. In other words, if a voltage of 5xcx9c7V is applied to a selected bit line B/L and a voltage of 9xcx9c12V is applied to a selected word line W/L used as the control gate 14 and a voltage of 0V is applied to the common source line CSL and the semiconductor substrate 10, some of the channel hot electrons is implanted into the floating gate 12 through the tunnel oxide film 11 by means of a gate electric field, so that a programming operation can be performed.
The erase operation is one to discharge electrons of the floating gate 12 to lower the threshold voltage Vth of the cell MC to a voltage of around 2V being an initial Vth value. In other words, if a selected bit line W/L is floated, a voltage of 12Vxcx9c15V is applied to the common source line CSL, a negative voltage of xe2x88x928V is applied to the word lines W/L used as the control gate 14 and a positive voltage of 8V is applied to the semiconductor substrate 10, electrons within the floating gate 12 are discharged into the source region 15 by means of the difference in the voltage between the floating gate 12 and the source region 15 in the F-N tunneling effect through the tunnel oxide film 11 of about 100 xc3x85, so that an erase operation can be performed.
The erase operation adopts a batch block erase mode by which several hundredsxcx9cseveral thousands of bits including a plurality of the word lines W/L and bit lines B/L are processed in a single block.
A reading operation detects whether a current path is generated through erase and program cells by applying a voltage of around 1V to a selected bit line B/L and a voltage of 4xcx9c5V to the word line W/L. The NOR-type the flash memory cell having this structure, however, has a disturbance phenomenon by means of over-erase. Over-erase means a phenomenon that an erase threshold voltage is lowered to 0V since a tunneling electric field is changed due to process defect in the unit cell, deterioration of the tunnel oxide film, oxidization of a tunnel edge and the like, while the threshold voltage of a normal erase cell is 2V. Generally, upon a programming operation, a selected cell must be programmed by generation of current through only the selected cell connected to a selected bit line to which programming voltage of 6V is applied and a selected word line to which a voltage of 12V is applied. If there is an over-erased cell in a non-selected word line to which a voltage of 0V is applied, however, the amount of current through a selected cell is reduced since a bit line voltage is discharged through a non-selected cell due to the threshold voltage of 0V. Due to this, there is a problem that the selected cell is not programmed since generation of hot electrons necessary for programming is prohibited. Further, upon a reading operation, there is a problem that a flow of current through an over-erased cell erroneously reads the selected cell as an erase state even when the selected is at a programming state due to abnormal current path through a non-selected over-erased cell.
In order to prevent over-erase of the cell as above, a conventional flash cell performs a pre-programming operation in order to match the threshold voltage of an initial cell to a certain degree and performs a post-programming operation being a soft program process in order to remove over-erased cell even after the erase operation is completed. This method, however, additionally requires a pre-programming S31 and a pre-programming verification S32, which are continued until the programming state is verified, and a post-programming S35 and a post-programming verification S36, which are continued until an over-erased cell is removed, as shown in FIG. 3 in addition to erase and erase verification algorithm. Therefore, this method degrades time efficiency in the cell erase operation. In addition, as current rarely flows in the F-N tunneling mode used upon an erase of the flash cell S33, the actually consumed power is not great. However, as current of over 200 xcexcA per single cell flows in the pre-programming S31 and current of over 200 xcexcA per bit line B/L flows in the pre-programming S35, the actually consumed power is increased within the algorithms S31 and S35 for preventing over-eras not the erase S33. Further, a conventional erase algorithm requires additional peripheral circuit for the post-programming and must simultaneously drive a positive charge pump circuit as well as a negative charge pump circuit, upon an erase operation. Therefore, the conventional erase algorithm consumes a lot of power since additional current is generated in the peripheral circuit block driven by an internal clock.
The present invention is contrived to solve the above problems and an object of the present invention is to provide a flash memory device in which a capacitor of a given capacitance is connected between a bit line connected to a drain region and a ground line within a flash cell array, and method of erasing the same, capable of reducing the time and power consumption in the cell erase operation by accelerating an increase of hot carriers generated in a diode reverse-bias state between the drain region and a semiconductor substrate upon an erase operation of the cell to solve over-erase or non-erase of the cell.
In order to accomplish the above object, a flash memory device according to the present invention is characterized in that it a memory cell array in which a plurality of memory cells are each connected between a plurality of word lines and a plurality of bit lines, a plurality of switching means each connected to said bit lines, and a capacitor connected between the plurality of the switching means and grounds.
Further, a flash memory device having a memory cell array in which a plurality of memory cell are connected between a plurality of word lines and a plurality of bit lines, respectively, is characterized in that upon an erase operation of the memory cell, a capacitor is connected between the plurality of the bit lines and grounds in order to prevent over-erase and non-erase.
Further, a method of erasing a flash memory cell including a floating gate and a control gate stacked on a semiconductor substrate, and source and drain formed in the semiconductor substrate on both sides of a floating gate is characterized in that it comprises performing an erase operation as electrons injected into the floating gate are discharged through the semiconductor substrate, by applying respective erase bias voltages to the control gate, the source and drain, and the semiconductor substrate, wherein hot carriers are generated in the semiconductor substrate depending on an increase of current by a capacitance between the drain and the ground and the generated hot carriers are injected into the floating gate, thus preventing over-erase and non-erase.